1. Technical Field
The disclosure relates generally to integrated circuits (ICs), and more particularly, to design structures, method and systems of powering on an integrated circuit (IC).
2. Background Art
Use of integrated circuits (IC) is ubiquitous. While the potential markets for products derived from a semiconductor technology have increased, so have the costs associated with bringing a semiconductor circuit family and/or IC to market. Use of today's IC technologies in such a diverse product set has forced an increase in operational temperature range from 0° C. to 100° C. in prior technologies to a wider temperature range from −55° C. to 125° C. in present technologies. For a typical present generation semiconductor technology, this temperature envelope expansion results in a change in the temperature-driven threshold voltage (Vt) variance of transistors from less than 70 millivolts to greater than 125 millivolts. The increase in Vt variance coupled with the scaling of supply voltage at a greater rate than Vt in succeeding technologies may result in circuits with functionality problems or poor performance characteristics over one or more process/voltage/temperature extremes. Traditionally, in the circuit design process, these functionality and performance problems result in substantial increases in design time, cost and risk and may add weeks to months to the design cycle for complex circuit functions.
Furthermore, the cost of supporting a wide temperature range does not stop at circuit design level, but continues to add cost and schedule delay in the design of the ICs which utilize the circuits. Here, support for a wide temperature range puts pressure on timing closure of critical paths within the IC, forcing iterative synthesis/optimization, circuit placement and routing. Colder temperatures speed semiconductor performance which stresses hold time specifications in which the time data must remain valid after a clock edge has locked the data into a sequential latch element. Chip-level designers are required to correct hold-time problems by adding additional buffering delays in the logic path to slow the data arrival at the sequential element. While necessary to prevent early-mode timing problems, these buffers consume space and power, and in some instances, cause timing problems during closure under worst case process/voltage/temperature conditions. In many cases resolving chip-level timing issues caused by increases in the temperature envelope may result in a final IC that operates at higher power and is larger, and as a result more costly to manufacture than an IC without the requirement of a wide operational temperature range.
While the high side of the temperature range is often set by the anticipated power density of ICs manufactured in a technology and the thermal limitations of semiconductor packaging, the low side of the temperature range is most often set by the external environment temperature at the moment the IC is powered-on, which is outside the control of the circuit, IC or system designer.